1. Field of the Invention
The present invention relates to a control system for controlling a signal processor command (called SIGP command hereinafter) between central processor units (CPUs) in a system having a plurality of CPUs and a memory control unit (MCU) internally equipped with a SIGP command control apparatus and more particularly to a control system for minimizing the number of signal lines and for determining a priority in a reasonable manner.
2. Description of the Related Art
In a system comprising a plurality of CPUs, a system is required for communicating between them.
It may be necessary to inquire whether or not a requested process can be executed, or it may be necessary to interrupt an already-requested process.
In such a case, the CPU sends a SIGP command to a CPU on the other party and determines the state of the requested process based on the response signal. The control system for controlling such a SIGP command is usually provided within a memory control apparatus.
FIG. 1 shows a block diagram representing a conventional system for controlling a SIGP command.
The SIGP request from CPU0 or CPU1 is set in port 1 or 2. The priority is then determined by first priority circuit 5 and transmitted to port 7 and the remote system console interface (RSCI) apparatus.
The SIGP request from the remote system console interface (RSCI) apparatus is set in port 8 and the priority between ports 8 and 7 is determined by second priority circuit 11.
The priority of the master system is higher in second priority circuit 11. Thus, when no SIGP request exists in the port of the master system, the port of the slave system is selected. When the local system site is selected by first priority circuit 5 and second priority circuit 11, register 16 (BUSY 1/2) is set. In addition, register 17 (SIG-CPU) is set corresponding to CPU-ID of the CPU selected by the first priority circuit and second priority circuit, and a COMMAND-ACK signal is transmitted to the corresponding CPU through port 15.
The CPU (source CPU) for receiving the COMMANDACK signal then transmits command data by the DATA-OUT bus at a certain timing. This data is set in register 3 or 4 and the data selected by selector 6 is transmitted to register 9 and the remote system console interface (RSCI) apparatus. Command data from the remote system console interface (RSCI) apparatus is set in register 10 and an output from both register 10 and register 9 is selected by selector 12 to be applied to address check circuit 13 and selector 14.
Address check circuit 13 determines the data's destination CPU and set register 18 (SIGNALED-CPU). Register 18 stores a flag of CPU 0/1 upon a transmission of COMMAND-IN (port 19) and upon a transmission of DATA-IN (registers 20 and 21). Address check circuit 13 receives a CPU 0/1 on-line signal, CPU 0/1 a floating CPU address signal and a power ready signal. Then it transmits a COMMAND-IN signal through port 19 and a DATA-IN signal through registers 20 or 21, to the corresponding CPU.
Thereafter, the CPU receiving COMMAND-IN transmits the status data via a STATUS-OUT bus and a DATA-OUT bus at a certain timing. The status data is transmitted to the source CPU through register 3 or 4, selector 6, register 9 or 10, selectors 12 and 14 and, register 20 or 21 by referring to register 17 (SIGNALING-CPU). Selector 12 receives DATA-OUT/STATUS-OUT, outputs STATUS-OUT to address check circuit 13 and outputs DATA-OUT/STATUS-OUT to selector 14. Selector 14 receives DATA-OUT from address check circuit 13. Selector 14 performs a selection using the same destination CPU-ID as register 18 in case of a command, and using the same REQUEST source CPU-ID as register 87 in case of a status.
In the conventional process system of the SIGP command, BUSY1/BUSY2 of register 16 is "on" only when the priority is obtained by both the first priority circuit and the second priority circuit. In other words, BUSY1/BUSY2 of register 16 is not set when the priority is not obtained by the second priority circuit. Therefore, when the priority can be obtained by a first access of the local system in the first priority circuit but a second access of the remote system is selected in the second priority circuit, then the first access is kept waiting in the first priority circuit.
Therefore, in order to avoid the situation in which a third access having a lower priority than the first access is selected in the first priority circuit while the first access is kept waiting, the priority in the first priority circuit should be fixed. For example, the younger numbered CPU always has the priority in the first priority circuit.
Therefore, in order to effectively obtain the priority order between CPUs, the priority may be given interchangeably to CPU0 or CPU1. Then there is a problem that when priority is obtained by the remote system in the second priority circuit and the process is returned to the first priority circuit, CPU1, which is different from CPU0 previously selected, is selected and after the process completion, priority is again given to the remote system. Thus, during the period in which priority should be given to CPU 0 in the first priority circuit, priority is given to the remote system in the second priority circuit. Then, when priority is returned to the local system in the second priority circuit, priority is again returned to CPU 1 in the first priority circuit. Thus, priority of CPU 1 is always maintained although priority is alternately changed in the first priority circuit. Thus, the same priority is given to the same CPU.
In the prior art system, respective central processing apparatuses and the memory control apparatuses require various control signals. When the scale of the system is large and thus, the number of CPUs and MCUs is large, a lot of control lines are required. This causes great difficulty in constructing and processing the system.